1. Field of the Invention
The present disclosure herein relates to methods of fabricating a semiconductor device and, more particularly, to methods of fabricating a semiconductor device including metal gate electrodes.
2. Description of the Related Art
Complementary metal-oxide-semiconductor (CMOS) integrated circuits have been widely employed to reduce power consumption of semiconductor devices. The CMOS integrated circuits comprise N-channel MOS transistors and P-channel MOS transistors.
As the semiconductor devices become more highly integrated, channel lengths of the N-channel MOS transistors and the P-channel MOS transistors have been gradually reduced. That is, as the integration density of the semiconductor devices increases, widths of gate electrodes of the MOS transistors have been reduced. In this case, the electrical resistance of the gate electrodes may increase to degrade performance of the semiconductor devices.
Recently, methods of forming the gate electrodes using a metal layer have been proposed in order to reduce the electrical resistance of the gate electrodes. However, in the event that the gate electrodes are formed of a metal layer, it may be difficult to pattern the metal layer using a photolithography and etching technique. Thus, a damascene technique may be employed to form metal gate electrodes without use of the photolithography and etching technique. The metal gate electrodes of the N-channel MOS transistors may be formed of a metal layer having a different work function from the metal gate electrodes of the P-channel MOS transistors. This is for optimizing threshold voltage characteristics of the N-channel MOS transistors and the P-channel MOS transistors.
In order to meet the requirements described above, it may be necessary to form a metal layer on a substrate including an N-channel MOS transistor region and a P-channel MOS transistor region and to selectively etch the metal layer in the N-channel MOS transistor region (or the P-channel MOS transistor region). A photoresist pattern may be used as an etching mask to selectively etch a portion of the metal layer. The photoresist pattern may be formed using an exposure process to selectively expose a portion of a photoresist layer to a specific light and a developing process to selectively remove the exposed portion of the photoresist layer. When the exposed photoresist layer is located in a narrow and deep groove, it may be difficult to completely remove the exposed photoresist layer. As a result, there may be limitations in optimizing characteristics of the CMOS integrated circuits and improving yield of the semiconductor devices.